Junior at UT Dallas designing full-custom silicon, high-voltage PCBs for our Formula SAE car, and the occasional SDR signal pipeline. I like problems that span transistor to firmware.
↳ Get in touchI build at the seam between hardware and software — places where a misaligned bit or a 5 ns timing slip is the whole story. My favorite work right now is full-custom VLSI design, the kind that starts with a Verilog RTL and ends with a clean DRC/LVS report on a GDSII layout.
Outside the EDA tools, I sit on the electrical side of Dallas Formula Racing, where I design and validate the high-voltage PCBs that keep our electric car safe and moving. The motorsport context forces a different kind of rigor — fault response budgets measured in milliseconds, safety rules that don't bend.
I'm looking for a summer 2026 internship in VLSI, ASIC verification, or hardware design. I'm happiest in environments where the work is technical, the feedback is fast, and someone has a logic analyzer plugged in.
A full-custom digital VLSI controller for an automotive turn-signal system, designed end-to-end on a custom 65 nm standard-cell library. FSM + 45-bit ripple-carry clock divider drive four sweeping 3-LED clusters. Closed with zero DRC/LVS errors and +14.47 ns of timing slack at a 60 ns clock; total power 0.0356 mW.
Ground-up CPU and instruction set designed under a strict embedded constraint sheet — 29-bit instructions, 24-bit data bus, 8-register file, reverse-endian arrays, and a 3-state multi-cycle FSM. Solved two nasty pipeline hazards (regfile race + DMEM store timing) and validated end-to-end with two custom assembly programs: C = A + B → 42 and Σ i = 0..10 → 55.
A purely analog brake/throttle plausibility device for our 2026 FSAE Electric car — no microcontroller, no firmware, just discrete CMOS gates, an NE555 RC delay, and a latching SR shutdown. Cut random hardware failures 70% and false triggers 90% versus the previous RC-only design. Currently moving from breadboard to Altium PCB.
Python signal-processing pipeline that captures live FM broadcasts off an RTL-SDR and decodes Radio Data System messages — I/Q acquisition, filtering, synchronization, demodulation. Antenna parameters tuned with a NanoVNA to hold reception stable in low-SNR conditions.
Led a 6-engineer team designing a container-mounted solar power plant for an atmospheric water generator deployed in Piura, Peru. Re-baselined a 40-ft prior design into a 20-ft container with 17 bifacial panels (10.37 kW), six 48 V LiFePO₄ batteries, and two paralleled MPPT inverters — all locally sourceable in Peru and within a $1k design-phase budget.
Validating the digital oscillator + divider on the bench; targeting 2026 FSAE Electric competition rules pass.
Improving sync recovery in low-SNR captures and characterizing reception with a tuned NanoVNA sweep.
Reading about scan, ATPG, and JTAG-based debug workflows on real automotive parts.